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Power gating architecture implementation inside clock period to reduce power
Nath, Debanjali, Choudhury, Priyanka, Nag, Abhishek, Pradhan, Sambhu NathVolume:
6
Year:
2014
Language:
english
Journal:
International Journal of Computer Aided Engineering and Technology
DOI:
10.1504/ijcaet.2014.063118
File:
PDF, 229 KB
english, 2014