Analysis of high-k spacer on symmetric underlap DG-MOSFET...

Superlattices and Microstructures 2016 / 09 Vol. 97

Analysis of high-k spacer on symmetric underlap DG-MOSFET with Gate Stack architecture

Das, Rahul, Chakraborty, Shramana, Dasgupta, Arpan, Dutta, Arka, Kundu, Atanu, Sarkar, Chandan K.
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Volume:
97
Language:
english
Journal:
Superlattices and Microstructures
DOI:
10.1016/j.spmi.2016.07.003
Date:
September, 2016
File:
PDF, 2.75 MB
english, 2016
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