[IEEE 2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) - Hsinchu, Taiwan (2016.4.25-2016.4.27)] 2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) - Interference-aware Batch Memory Scheduling in heterogeneous multicore architecture
Lu, Chun-Hsien, Chao, Hung-Lin, Song, Yi-Chien, Hsiung, Pao-AnnYear:
2016
Language:
english
DOI:
10.1109/vlsi-dat.2016.7482559
File:
PDF, 285 KB
english, 2016