Process optimizations to recessed e-SiGe source/drain for...

Solid-State Electronics 2016 / 09 Vol. 123

Process optimizations to recessed e-SiGe source/drain for performance enhancement in 22nm all-last high-k/metal-gate pMOSFETs

Qin, Changliang, Wang, Guilei, Hong, Peizhen, Liu, Jinbiao, Yin, Huaxiang, Yin, Haizhou, Ma, Xiaolong, Cui, Hushan, Lu, Yihong, Meng, Lingkuan, Xiang, Jinjuan, Zhong, Huicai, Zhu, Huilong, Xu, Qiuxia,
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Volume:
123
Language:
english
Journal:
Solid-State Electronics
DOI:
10.1016/j.sse.2016.05.017
Date:
September, 2016
File:
PDF, 2.46 MB
english, 2016
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