A Power-and-Area Efficient 10 x 10 Gb/s Bootstrap...

  • Main
  • 2016
  • A Power-and-Area Efficient 10 x 10 Gb/s Bootstrap...
IEEE Journal of Solid-State Circuits 2016

A Power-and-Area Efficient 10 x 10 Gb/s Bootstrap Transceiver in 40 nm CMOS for Referenceless and Lane-Independent Operation

Lee, Joon-Yeong, Han, Kwangseok, Yoon, Taehun, Kim, Taeho, Lee, Sang-Eun, Lee, Jeong-Sup, Park, Jinho, Bae, Hyeon-Min
How much do you like this book?
What’s the quality of the file?
Download the book for quality assessment
What’s the quality of the downloaded files?
Year:
2016
Language:
english
Journal:
IEEE Journal of Solid-State Circuits
DOI:
10.1109/JSSC.2016.2590550
File:
PDF, 5.32 MB
english, 2016
Conversion to is in progress
Conversion to is failed