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IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2016

Eliminating Timing Errors Through Collaborative Design to Maximize the Throughput

Li, Zhan-Hui, Zhu, Tao-Tao, Chen, Zhi-Jian, Meng, Jian-Yi, Xiang, Xiao-Yan, Yan, Xiao-Lang
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Year:
2016
Language:
english
Journal:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOI:
10.1109/tvlsi.2016.2587810
File:
PDF, 4.97 MB
english, 2016
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