Area Efficient VLSI Architecture for Square Root Carry Select Adder Using Zero Finding Logic
Kandula, Bala Sindhuri, Vasavi, K. Padma, Prabha, I. SantiVolume:
89
Year:
2016
Language:
english
Journal:
Procedia Computer Science
DOI:
10.1016/j.procs.2016.06.028
File:
PDF, 1014 KB
english, 2016