A 5.5 mW ADPLL-Based Receiver With a Hybrid Loop...

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IEEE Journal of Solid-State Circuits 2016

A 5.5 mW ADPLL-Based Receiver With a Hybrid Loop Interference Rejection for BLE Application in 65 nm CMOS

Sai, Akihide, Okuni, Hidenori, Ta, Tuan Thanh, Kondo, Satoshi, Tokairin, Takashi, Furuta, Masanori, Itakura, Tetsuro
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Year:
2016
Language:
english
Journal:
IEEE Journal of Solid-State Circuits
DOI:
10.1109/jssc.2016.2603993
File:
PDF, 3.77 MB
english, 2016
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