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Ultra-low power pass-transistor-logic-based delay line design for sub-threshold applications
Tadros, R.N., Dasari, N., Beerel, P.A.Volume:
52
Language:
english
Journal:
Electronics Letters
DOI:
10.1049/el.2016.3240
Date:
November, 2016
File:
PDF, 173 KB
english, 2016