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A Novel Test Compression Algorithm for Analog Circuits to Decrease Production Costs
Ahmadyan, Seyed Nematollah, Natarajan, Suriyaprakash, Vasudevan, ShobhaLanguage:
english
Journal:
Integration, the VLSI Journal
DOI:
10.1016/j.vlsi.2016.10.010
Date:
November, 2016
File:
PDF, 2.93 MB
english, 2016