A DMR logic for mitigating the SET induced soft errors in...

IEICE Electronics Express 2016 Vol. 13; Iss. 2

A DMR logic for mitigating the SET induced soft errors in combinational circuits

Jiajin, Zhang, Housen, Yang, Yankang, Du, Quan, Gao, Lin, Peng, Yue, Zhang, Chen, Lichang
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Volume:
13
Year:
2016
Language:
english
Journal:
IEICE Electronics Express
DOI:
10.1587/elex.12.20150927
File:
PDF, 1.34 MB
english, 2016
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