Dual priority congestion aware shared-resource...

IEICE Electronics Express 2016 Vol. 13; Iss. 7

Dual priority congestion aware shared-resource Network-on-Chip architecture

Shu, Hao, Shi, Jiangyi, Ma, Peijun, Gu, Huaxi, Pan, Weitao, Yang, Lin-an
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Volume:
13
Year:
2016
Language:
english
Journal:
IEICE Electronics Express
DOI:
10.1587/elex.13.20160142
File:
PDF, 2.13 MB
english, 2016
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