CMOS latch bit-cell array for low-power SRAM design

IEICE Electronics Express 2010 Vol. 7; Iss. 15

CMOS latch bit-cell array for low-power SRAM design

Chung, Yeonbae, Cheng, Weijie
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Volume:
7
Year:
2010
Language:
english
Journal:
IEICE Electronics Express
DOI:
10.1587/elex.7.1145
File:
PDF, 1.34 MB
english, 2010
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