Energy-efficient High-level Synthesis for HDR Architectures...

IPSJ Transactions on System LSI Design Methodology 2013 Vol. 6

Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling

Akasaka, Hiroyuki, Abe, Shin-ya, Yanagisawa, Masao, Togawa, Nozomu
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Volume:
6
Year:
2013
Language:
english
Journal:
IPSJ Transactions on System LSI Design Methodology
DOI:
10.2197/ipsjtsldm.6.101
File:
PDF, 980 KB
english, 2013
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