An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation
Higami, Yoshinobu, Saluja, Kewal K., Takahashi, Hiroshi, Kobayashi, Sin-ya, Takamatsu, YuzoVolume:
2
Year:
2009
Language:
english
Journal:
IPSJ Transactions on System LSI Design Methodology
DOI:
10.2197/ipsjtsldm.2.250
File:
PDF, 304 KB
english, 2009