Design of 65nm Sub-Threshold SRAM Using the Bitline Leakage...

IEICE Transactions on Electronics 2012 Vol. E95-C; Iss. 1

Design of 65nm Sub-Threshold SRAM Using the Bitline Leakage Prediction Scheme and the Non-trimmed Sense Amplifier

WANG, Jinn-Shyan, CHANG, Pei-Yao, LIN, Chi-Chang
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Volume:
E95-C
Year:
2012
Language:
english
Journal:
IEICE Transactions on Electronics
DOI:
10.1587/transele.e95.c.172
File:
PDF, 1.26 MB
english, 2012
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