An integrated DFT solution for power reduction in scan test...

Integration, the VLSI Journal 2017 / 03 Vol. 57

An integrated DFT solution for power reduction in scan test applications by low power gating scan cell

Naeini, Mahshid Mojtabavi, Dass, Sreedharan Baskara, Ooi, Chia Yee, Yoneda, Tomokazu, Inoue, Michiko
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Volume:
57
Language:
english
Journal:
Integration, the VLSI Journal
DOI:
10.1016/j.vlsi.2016.12.009
Date:
March, 2017
File:
PDF, 2.40 MB
english, 2017
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