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Fast Multiplier Generator for FPGAs with LUT based Partial...

Integration, the VLSI Journal 2017 / 03 Vol. 57

Fast Multiplier Generator for FPGAs with LUT based Partial Product Generation and Column/row Compression

Kakacak, Ahmet, Guzel, Aydin Emre, Cihangir, Ozan, Gören, Sezer, Ugurdag, H. Fatih
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Volume:
57
Language:
english
Journal:
Integration, the VLSI Journal
DOI:
10.1016/j.vlsi.2016.12.012
Date:
March, 2017
File:
PDF, 1.15 MB
english, 2017
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