[IEEE 2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) - Bangalore, India (2016.5.20-2016.5.21)] 2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) - VLSI architecture for delay efficient 32-bit multiplier using vedic mathematic sutras
Ram, G. Challa, Rani, D. Sudha, Balasaikesava, R., Sindhuri, K. BalaYear:
2016
Language:
english
DOI:
10.1109/RTEICT.2016.7808160
File:
PDF, 6.60 MB
english, 2016