![](/img/cover-not-exists.png)
ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures
Wang, Po-Hao, Chien, Yung-Chen, Tsai, Shang-Jen, Lin, Xuan-Yu, Tanjung, Rizal, Lin, Yi-Sian, Syu, Shu-Wei, Lin, Tay-Jyi, Wang, Jinn-Shyan, Chen, Tien-FuYear:
2017
Language:
english
Journal:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOI:
10.1109/TVLSI.2016.2642170
File:
PDF, 4.39 MB
english, 2017