[IEEE 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) - Storrs, CT, USA (2016.9.19-2016.9.20)] 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) - On meta-obfuscation of physical layouts to conceal design characteristics
Patil, Vinay C., Vijayakumar, Arunkumar, Kundu, SandipYear:
2016
Language:
english
DOI:
10.1109/dft.2016.7684087
File:
PDF, 559 KB
english, 2016