Compact Modeling of Charge, Capacitance, and Drain Current...

IEEE Transactions on Nanotechnology 2017 / 3 Vol. 16; Iss. 2

Compact Modeling of Charge, Capacitance, and Drain Current in III–V Channel Double Gate FETs

Yadav, Chandan, Agrawal, Mayank, Agarwal, Amit, Chauhan, Yogesh Singh
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Volume:
16
Language:
english
Journal:
IEEE Transactions on Nanotechnology
DOI:
10.1109/TNANO.2017.2669092
Date:
March, 2017
File:
PDF, 712 KB
english, 2017
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