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[IEEE 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) - Rennes, France (2016.10.12-2016.10.14)] 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) - Hardware architecture for lowering the error floor of LTE turbo codes
Tonnellier, Thibaud, Leroux, Camille, Le Gal, Bertrand, Jego, Christophe, Gadat, Benjamin, Van Wambeke, NicolasYear:
2016
Language:
english
DOI:
10.1109/dasip.2016.7853805
File:
PDF, 307 KB
english, 2016