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SPIE Proceedings [SPIE SPIE Advanced Lithography - San Jose, California, United States (Sunday 26 February 2017)] Design-Process-Technology Co-optimization for Manufacturability XI - Stitching-aware in-design DPT auto fixing for sub-20nm logic devices
Capodieci, Luigi, Cain, Jason P., Choi, Soo-Han, Krishna K.V.V.S, Sai, Pemberton-Smith, DavidVolume:
10148
Year:
2017
Language:
english
DOI:
10.1117/12.2262836
File:
PDF, 380 KB
english, 2017