Through-Silicon Via Capacitance-Voltage Hysteresis Modeling for 2.5-D and 3-D IC
Kim, Dong-Hyun, Kim, Youngwoo, Cho, Jonghyun, Bae, Bumhee, Park, Junyong, Lee, Hyunsuk, Lim, Jaemin, Kim, Jonghoon J., Piersanti, Stefano, de Paulis, Francesco, Orlandi, Antonio, Kim, JounghoYear:
2017
Language:
english
Journal:
IEEE Transactions on Components, Packaging and Manufacturing Technology
DOI:
10.1109/TCPMT.2017.2670063
File:
PDF, 3.50 MB
english, 2017