A 65nm 0.08-to-680MHz Synthesizable MDLL with Nested-Delay...

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IEEE Transactions on Circuits and Systems II: Express Briefs 2017

A 65nm 0.08-to-680MHz Synthesizable MDLL with Nested-Delay Cell and Background Static Phase Offset Calibration

Chang, Dong-Jin, Seo, Min-Jae, Hong, Hyeok-Ki, Ryu, Seung-Tak
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Year:
2017
Language:
english
Journal:
IEEE Transactions on Circuits and Systems II: Express Briefs
DOI:
10.1109/TCSII.2017.2689029
File:
PDF, 1.22 MB
english, 2017
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