SPIE Proceedings [SPIE SPIE Advanced Lithography - San Jose, California, United States (Sunday 26 February 2017)] Design-Process-Technology Co-optimization for Manufacturability XI - The effect of patterning options on embedded memory cells in logic technologies at iN10 and iN7
Capodieci, Luigi, Cain, Jason P., Appeltans, Raf, Weckx, Pieter, Raghavan, Praveen, Kim, Ryoung-Han, Kar, Gouri Sankar, Furnémont, Arnaud, Van der Perre, Liesbet, Dehaene, WimVolume:
10148
Year:
2017
Language:
english
DOI:
10.1117/12.2255089
File:
PDF, 2.50 MB
english, 2017