Standby and dynamic power minimization using enhanced hybrid power gating structure for deep-submicron CMOS VLSI
Johannah, J. Jeba, Korah, Reeba, Kalavathy, Maria, Sivanandham,Volume:
62
Language:
english
Journal:
Microelectronics Journal
DOI:
10.1016/j.mejo.2017.02.003
Date:
April, 2017
File:
PDF, 1.15 MB
english, 2017