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SPIE Proceedings [SPIE SPIE Advanced Lithography - San Jose, California, United States (Sunday 26 February 2017)] Design-Process-Technology Co-optimization for Manufacturability XI - IR-drop analysis for validating power grids and standard cell architectures in sub-10nm node designs
Capodieci, Luigi, Cain, Jason P., Ban, Yongchan, Wang, Chenchen, Zeng, Jia, Kye, JongwookVolume:
10148
Year:
2017
Language:
english
DOI:
10.1117/12.2258340
File:
PDF, 1.07 MB
english, 2017