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[IEEE 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE) - Lausanne, Switzerland (2017.3.27-2017.3.31)] Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 - A generic topology selection method for analog circuits with embedded circuit sizing demonstrated on the OTA example
Gerlach, Andreas, Scheible, Juergen, Rosahl, Thoralf, Eitrich, Frank-ThomasYear:
2017
Language:
english
DOI:
10.23919/DATE.2017.7927115
File:
PDF, 324 KB
english, 2017