Performance Analysis of Schielded Channel Double Gate...

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International Journal of Electronics Letters 2017 / 05

Performance Analysis of Schielded Channel Double Gate Junctionless and Junction MOS-Transistor

Wagaj, S.C., Patil, Shailaja, Chavan, Y.V.
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Language:
english
Journal:
International Journal of Electronics Letters
DOI:
10.1080/21681724.2017.1335785
Date:
May, 2017
File:
PDF, 1.52 MB
english, 2017
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