A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM...

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IEEE Transactions on Circuits and Systems I: Regular Papers 2017

A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS

Grover, Anuj, Visweswaran, G. S., Parthasarathy, Chittoor R., Daud, Mohammad, Turgis, David, Giraud, Bastien, Noel, Jean-Philippe, Miro-Panades, Ivan, Moritz, Guillaume, Beigne, Edith, Flatresse, Phil
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Year:
2017
Language:
english
Journal:
IEEE Transactions on Circuits and Systems I: Regular Papers
DOI:
10.1109/tcsi.2017.2705116
File:
PDF, 3.30 MB
english, 2017
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