[IEEE 2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) - Hsinchu, Taiwan (2017.4.24-2017.4.27)] 2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) - Low-latency Voltage-Racing Winner-Take-All (VR-WTA) circuit for acceleration of learning engine
Wu, Chia-Heng, Chen, Ting-Sheng, Lee, Ding-Yuan, Liu, Tsung-Te, Wu, An-YeuYear:
2017
Language:
english
DOI:
10.1109/VLSI-DAT.2017.7939641
File:
PDF, 1.22 MB
english, 2017