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Fractional-N DPLL-Based Low-Power Clocking Architecture for 1-14 Gb/s Multi-Standard Transmitter
Hossain, Masum, El-Halwagy, Waleed, Hossain, AKM Delwar, Aurangozeb,Year:
2017
Language:
english
Journal:
IEEE Journal of Solid-State Circuits
DOI:
10.1109/JSSC.2017.2715160
File:
PDF, 7.13 MB
english, 2017