Effect of interface traps for ultra-thin high-k gate...

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Microelectronics Reliability 2017 / 7

Effect of interface traps for ultra-thin high-k gate dielectric based MIS devices on the capacitance-voltage characteristics

Hlali, Slah, Hizem, Neila, Militaru, Liviu, Kalboussi, Adel, Souifi, Abdelkader
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Language:
english
Journal:
Microelectronics Reliability
DOI:
10.1016/j.microrel.2017.06.056
Date:
July, 2017
File:
PDF, 2.21 MB
english, 2017
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