Numerical Investigation of High-Voltage Partial Buried...

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IEEE Transactions on Electron Devices 2017

Numerical Investigation of High-Voltage Partial Buried P/N-Layer SOI LDMOS

Hu, Yue, Gong, Yanfei, Liu, Huazhen, Xu, Qianqian, Zhao, Wen-Sheng, Wang, Jing, Wang, Ying, Wang, Gaofeng
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Year:
2017
Language:
english
Journal:
IEEE Transactions on Electron Devices
DOI:
10.1109/TED.2017.2724921
File:
PDF, 2.47 MB
english, 2017
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