A 0.5-V all-digital clock-deskew buffer with I/Q phase...

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Analog Integrated Circuits and Signal Processing 2017 / 6

A 0.5-V all-digital clock-deskew buffer with I/Q phase outputs

Tu, Yo-Hao, Liu, Jen-Chieh, Cheng, Kuo-Hsing, Hsu, Chih-Hsun
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Language:
english
Journal:
Analog Integrated Circuits and Signal Processing
DOI:
10.1007/s10470-017-1005-4
Date:
June, 2017
File:
PDF, 2.96 MB
english, 2017
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