[IEEE 2017 Symposium on VLSI Technology - Kyoto, Japan (2017.6.5-2017.6.8)] 2017 Symposium on VLSI Technology - Impact of strain on access resistance in planar and nanowire CMOS devices
Berthelon, R., Andneu, F., Triozon, F., Casse, M., Bourdet, L., Ghibaudo, G., Rideau, D., Niquet, Y. M., Barraud, S., Nguyen, P., Le Royer, C., Lacord, J., Tabone, C., Rozeau, O., Dutartre, D., ClaverYear:
2017
Language:
english
DOI:
10.23919/VLSIT.2017.7998180
File:
PDF, 860 KB
english, 2017