[IEEE 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) - Bochum, Germany (2017.7.3-2017.7.5)] 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) - Latency Aware Block Replacement for L1 Caches in Chip Multiprocessor
Das, Shirshendu, Kapoor, Hemangee K.Year:
2017
Language:
english
DOI:
10.1109/ISVLSI.2017.40
File:
PDF, 821 KB
english, 2017