Study of Gaussian Doped Double Gate JunctionLess (GD-DG-JL)...

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Superlattices and Microstructures 2017 / 9

Study of Gaussian Doped Double Gate JunctionLess (GD-DG-JL) Transistor Including Source Drain Depletion Length: Model for Sub-threshold Behavior

Kumari, Vandana, Kumar, Ayush, ManojSaxena,, Gupta, Mridula
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Language:
english
Journal:
Superlattices and Microstructures
DOI:
10.1016/j.spmi.2017.09.049
Date:
September, 2017
File:
PDF, 737 KB
english, 2017
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