[IEEE 2017 4th International Conference on Signal Processing and Integrated Networks (SPIN) - Noida, Delhi-NCR, India (2017.2.2-2017.2.3)] 2017 4th International Conference on Signal Processing and Integrated Networks (SPIN) - An efficient VLSI architecture for iterative logarithmic multiplier
Nandan, Durgesh, Kanungo, Jitendra, Mahajan, AnuragYear:
2017
Language:
english
DOI:
10.1109/SPIN.2017.8049986
File:
PDF, 279 KB
english, 2017