Architectural synthesis of high-level analogue VHDL-AMS descriptions using netlist extraction from parse trees
Doménech-Asensi, G., Kazmierski, T.J., Ruiz-Marin, J.D., Ruiz-Merino, R.Volume:
36
Year:
2000
Language:
english
Journal:
Electronics Letters
DOI:
10.1049/el:20001202
File:
PDF, 364 KB
english, 2000