Integration of low permittivity dielectric in Al dual damascene architecture for low parasitic on-chip interconnect applications
Zhao, B., Feiler, D., Liu, Q.Z., Nguyen, C.H., Brongo, M., Kuei, J., Ramanathan, V., Zhang, H., Wu, J., Rumer, M., Biberger, M.A., Sachan, V., James, D.Volume:
34
Year:
1998
Language:
english
Journal:
Electronics Letters
DOI:
10.1049/el:19980951
File:
PDF, 321 KB
english, 1998