Evolutionary Computation Based Sizing Technique of Nulling...

International Journal of High Speed Electronics and Systems 2017 / 12 Vol. 26; Iss. 4

Evolutionary Computation Based Sizing Technique of Nulling Resistor Compensation Based CMOS Two-Stage Op-Amp Circuit

De, Bishnu Prasad, Maji, Kanchan Baran, Kar, Rajib, Mandal, Durbadal, Ghoshal, Sakti Prasad
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Volume:
26
Language:
english
Journal:
International Journal of High Speed Electronics and Systems
DOI:
10.1142/S0129156417400213
Date:
December, 2017
File:
PDF, 279 KB
english, 2017
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