LP-HS Logic Evaluation on TSMC 0.18μm CMOS Technology

International Journal of High Speed Electronics and Systems 2017 / 12 Vol. 26; Iss. 4

LP-HS Logic Evaluation on TSMC 0.18μm CMOS Technology

Saha, Aloke, Kumar, Sushil, Das, Debajit, Chakraborty, Mrinmoy
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Volume:
26
Language:
english
Journal:
International Journal of High Speed Electronics and Systems
DOI:
10.1142/S0129156417400249
Date:
December, 2017
File:
PDF, 2.33 MB
english, 2017
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