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Integration, the VLSI Journal 2017 / 12

Metastability immune and area efficient error masking flip-flop for timing error resilient designs

Sannena, Govinda, Das, Bishnu Prasad
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Language:
english
Journal:
Integration, the VLSI Journal
DOI:
10.1016/j.vlsi.2017.11.006
Date:
December, 2017
File:
PDF, 1.79 MB
english, 2017
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