BIST-Based Low Power Test Vector Generator and Minimizing...

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Journal of Circuits System and Computers 2017 / 09

BIST-Based Low Power Test Vector Generator and Minimizing Bulkiness of VLSI Architecture

Praveen, J., Shanmukha Swamy, M. N.
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Language:
english
Journal:
Journal of Circuits, Systems and Computers
DOI:
10.1142/s0218126618500780
Date:
September, 2017
File:
PDF, 433 KB
english, 2017
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