Real-time FPGA design for the L0-trigger of the RICH...

Journal of Instrumentation 2017 / 01 Vol. 12; Iss. 1

Real-time FPGA design for the L0-trigger of the RICH detector of the NA62 experiment at CERN SPS

Barbanera, M., Gonnella, F.
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Volume:
12
Language:
english
Journal:
Journal of Instrumentation
DOI:
10.1088/1748-0221/12/01/C01023
Date:
January, 2017
File:
PDF, 2.25 MB
english, 2017
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