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[IEEE 2017 Symposium on VLSI Circuits - Kyoto, Japan (2017.6.5-2017.6.8)] 2017 Symposium on VLSI Circuits - A 28.05Gb/s transceiver using quarter-rate triple-speculation hybrid-DFE receiver with calibrated sampling phases in 32nm CMOS
Gangasani, Gautam, Bulzacchelli, John F., Wielgos, Michael, Kelly, William, Sharma, Vivek, Prati, Andrea, Cervelli, Giovanni, Gardellini, Daniele, Baecher, Matthew, Shannon, Michael, Beukema, Troy, GaYear:
2017
Language:
english
DOI:
10.23919/VLSIC.2017.8008527
File:
PDF, 623 KB
english, 2017