A Pattern Recognition Mezzanine based on Associative Memory and FPGA technology for Level 1 Track Triggers for the HL-LHC upgrade
Magalotti, D., Alunni, L., Biesuz, N., Bilei, G.M., Citraro, S., Crescioli, F., Fanò, L., Fedi, G., Magazzù, G., Servoli, L., Storchi, L., Palla, F., Placidi, P., Rossi, E., Spiezia, A.Volume:
11
Language:
english
Journal:
Journal of Instrumentation
DOI:
10.1088/1748-0221/11/02/C02063
Date:
February, 2016
File:
PDF, 1.81 MB
english, 2016